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A/D 12-bit, Quad 1.3 Gsps or Dual 2.6 Gsps

  • FMC - VITA57.1 HPC Compliant
  • 2-Channels 12-bit, 2,6 Gsps A/D or
  • 4-Channels 12-bit, 1,3 Gsps A/D
  • SSMC Connectors
  • Conduction-cooled compliant

IC-ADC-FMCc - A/D Quad 12 bit Gsps FMC board

The IC-ADC-FMCc board is part of our Front End Processing product line to respond to the increasing demand in fast data sampling for embedded systems especially in the field of Software Radio, Radar and Electronic Warfare solutions.

The IC-ADC-FMCc is a VITA 57.1 FPGA Mezzanine Card (FMC).

It offers a flexible connectivity with our FPGA 3U and 6U Front End Processing boards running our Signal Processing Regerence Design (including signal acquisition, Processing DMA Engine, data storage, signal generation,…).

It thus allows customers to streamline development of high performance signal acquisition systems by concentrating their efforts on their most critical tasks.

Analog Inputs
Two ADC12d1600Texas Intruments ADCs with 12 bit resolution
4 channels with SSMC connectors
Input impedance 50 Ω AC or DC coupling
With AC coupling analog input bandwitdth (-3dB) 5- 2200 MHz. Full scale amplitude 800mV peak-peak
SNR : 58 dBFS @Fin = 400 MHz, 56 dBFS @Fin = 836 MHz, 54 dBFS @Fin = 1228 MHz
SFDR: 65 dBc @Fin = 400 MHz, 62 dBc @Fin = 836 MHz, 60 dBc @Fin = 1228 MHz
ENOB: 9.2 bit @Fin = 400 MHz, 8.7bit @Fin = 836 MHz, 8.5 bit @Fin = 1228 MHz

Sampling Clock (CKI) or Reference Input (REFI):
Clock device : TI LMK04828B with Clock Jitter Cleaner with Dual Loop PLLs
Sampling clock or reference input. SSMC connector, 50 Ω, AC coupled
Input level. Sine wave: 0 to +10dB. Square wave: LVPECL single ended
10 MHz to 750 MHz reference input when used as REFI
Max input frequency when used as CKI: >= 1300 MHz

Clocking options :
Directly driven on front panel (CKI)
Synthesized by on- board Dual PLL form front panel reference clock input (REFI)
Synthesized by on-board Dual PLL from reference clock input form FMC connector

Clock Output (CKO)
SSMC connector, 50 Ohm, AC coupled
800 mV peak-peak typ., square
300 to 1300 MHz

Trigger input
SSMC connector, 50 Ohm, AC/DC coupled. LVPCELor Single ended

ADC digital interface
12 LVDS data + 1 LVDS clock
Offset binary or 2’s complement

Board Electrical/environmental
12 LVDS data + 1 LVDS clock, offset binary or 2’s complement
Board Electrical/environmental 
FMC I/O voltage: VADJ=1.8V
Power dissipation: 13.5 W

Interface features

Front board. 7 x SSMC connectors
4 x Analog Inputs
One Clock input (CKI or REFI)
One Clock output
One Trigger Input

FMC connector according to VITA 57.1:
12 LVDS data + 1 LVDS clock per channel

IC-ADC-FMCc diagram - A/D 12-bit, Quad 1.3 Gsps or Dual 2.6 Gsps
IC-ADC-FMCc diagram - A/D 12-bit, Quad 1.3 Gsps or Dual 2.6 Gsps
Criterion Standard Extended Rugged Conduction-cooled 71°C Conduction-cooled 85°C
Coating Optional Yes Yes Yes Yes
Operat. Temp. 0 to 55°C -20 to 65°C -40°C to 71°C or 85°C (*) -40°C to 71°C
at the thermal interface (*)
-40°C to 85°C
at the thermal interface (*)
Rec. airflow 1 .. 2 m/s 2 .. 3 m/s 2 .. 5 m/s - -
Oper. HR% no cond. 5 to 90% 5 to 95% 5 to 95% 5 to 95% 5 to 95%
Storage Temp. -45°C to 85°C -45°C to 85°C -45°C to 100°C -45°C to 100°C -45°C to 100°C
Sinusoidal Vibr 2G [20..2000]Hz 2G [20..2000]Hz 5G [20..2000]Hz 5G [20..2000]Hz 5G [20..2000]Hz
Random Vibr 0.002g2 /Hz
0.002g2 /Hz
0.05g2 /Hz
0.1g2 /Hz
0.1g2 /Hz
Shock 1/2 Sin. 11ms 20G 20G 40G 40G 40G
(*) Temperature grades are subject to availability according to IC products. Please consult us.

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