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Products

IC-ADDA-FMCa

A/D 12-bit, Dual 1.6 Gsps (One 3.2 Gsps) D/A 14-bit, One 5.7 Gsps

  • FMC - VITA57.1 HPC Compliant
  • 1 Channel 12-bit, 3,2 Gsps A/D or
  • 2 Channels 12-bit, 1,6 Gsps A/D
  • 1 Channel 16-bit, 5,7 Gsps D/A
  • SSMC Connectors
  • Conduction-cooled compliant

IC-ADDA-FMCa - VITA  57.4  FMC

The IC-ADDA-FMCa board is part of our Front End Processing product line to respond to the increasing demand in fast data sampling for embedded systems especially in the field of Software-defined Radio, Radar and Electronic Warfare solutions.

Designed for applications where high data sampling is required, the IC-ADDA-FMCa is a VITA 57.1 FPGA Mezzanine Card (FMC). It offers a flexible connectivity with our FPGA 3U and 6U Front End Processing boards running our Signal Processing Regerence Design (including signal acquisition, Processing DMA Engine, data storage, signal generation,…) thus allowing customers to streamline development of high performance signal acquisition systems by concentrating their efforts on their most critical tasks.

Analog Inputs
One ADC12d1600 from Texas Instruments™ with 12 bit resolution
Sampling rate at 1.6 Gsps (3.2 Gsps interleaved)
2 channels with SSMC connectors
Input impedance 50 ? AC coupled
Analog input bandwitdth (-3dB) > 5-2200 MHz in Dual 1.6 Gsps channel configuration. Full scale  mplitude 800 mV peak-peak

Analog Outputs
One AD9129 Analog Devices™ DAC with 14 bit resolution
D/A sample rate : 2.85 GSPS digital input - 2.85 GSPS output (1x interpolation) - 5.7 GSPS output (2 x interpolations)
1 channel with SSMC connectors
Output impedance 50 Ohm AC coupled
Analog bandwitdth 1.1 GHz in 2 x interpolation mode; 1.4 GHz in baseband mode. Full scale amplitude 1 V peak-peak

Clocks
Sampling Clock (CKI) or Reference Clock (REFI) :
SSMC connector, 50 Ohm, AC coupled
Input level. Sine wave: 0 to +10dB. Square wave: LVPECL single ended
Frequency range: CKI up to 2850 MHz; REFI 10 MHz tp 250 MHz
Clock Output (CKO) :
SSMC connector, 50 ? , AC coupled
0.8 V peak-peak
500 MHz to 2580 MHz

Clocking options (for both A/D and D/A clocks): Clock tree is based on a dual PLL architecture
A/D and D/A sampling clocks are derived from either:
external front panel input (CKI) distributed to A/D - D/A
on-board synthesis from front panel reference input
on-board synthesis from on-board 10MHz TCXO

Trigger/Sync input
SSMC connector 50 ? DC coupled

ADC / DAC digital interface
ADC Output : LVDS – Dual data rate - 4 x 12 demuxed data bus. 800 Mbps per LVDS/ 400 MHz clock. Offset binary or two’s complement
DAC Input: LVDS – LVDS – Dual data rate – 2 x 14 LVDS data. 2.85 GSPS rate/ 1.425 Gbps/ 712.5 MHz clock. Binary or two’s complement

Board Electrical/environmental
VITA 57.1 HPC single width module with Region 1 and front I/O
Power dissipation: 8.5 W
FMC I/O voltage: VADJ= 1.8 or 2.5V
Air cooled, Rugged air cooled and conduction cooled

IC-ADDA-FMCa - VITA  57.4  FMC diagram
IC-ADDA-FMCa - VITA  57.4  FMC diagram
Criterion Standard Extended Rugged Conduction-cooled 71°C Conduction-cooled 85°C
Coating Optional Yes Yes Yes Yes
Operat. Temp. 0 to 55°C -20 to 65°C -40°C to 71°C or 85°C (*) -40°C to 71°C
at the thermal interface (*)
-40°C to 85°C
at the thermal interface (*)
Rec. airflow 1 .. 2 m/s 2 .. 3 m/s 2 .. 5 m/s - -
Oper. HR% no cond. 5 to 90% 5 to 95% 5 to 95% 5 to 95% 5 to 95%
Storage Temp. -45°C to 85°C -45°C to 85°C -45°C to 100°C -45°C to 100°C -45°C to 100°C
Sinusoidal Vibr 2G [20..2000]Hz 2G [20..2000]Hz 5G [20..2000]Hz 5G [20..2000]Hz 5G [20..2000]Hz
Random Vibr 0.002g2 /Hz
[10..2000]Hz
0.002g2 /Hz
[10..2000]Hz
0.05g2 /Hz
[10..2000]Hz
0.1g2 /Hz
[10..2000]Hz
0.1g2 /Hz
[10..2000]Hz
Shock 1/2 Sin. 11ms 20G 20G 40G 40G 40G
(*) Temperature grades are subject to availability according to IC products. Please consult us.

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