A/D 12-bit, Quad 1.3 Gsps or Dual 2.6 Gsps

Analog Inputs
Two ADC12d1600Texas Intruments ADCs with 12 bit resolution
4 channels with SSMC connectors
Input impedance 50 Ω AC or DC coupling
With AC coupling analog input bandwitdth (-3dB) 5- 2200 MHz. Full scale amplitude 800mV peak-peak
SNR : 58 dBFS @Fin = 400 MHz, 56 dBFS @Fin = 836 MHz, 54 dBFS @Fin = 1228 MHz
SFDR: 65 dBc @Fin = 400 MHz, 62 dBc @Fin = 836 MHz, 60 dBc @Fin = 1228 MHz
ENOB: 9.2 bit @Fin = 400 MHz, 8.7bit @Fin = 836 MHz, 8.5 bit @Fin = 1228 MHz

Clocks
Sampling Clock (CKI) or Reference Input (REFI):
Clock device : TI LMK04828B with Clock Jitter Cleaner with Dual Loop PLLs
Sampling clock or reference input. SSMC connector, 50 Ω, AC coupled
Input level. Sine wave: 0 to +10dB. Square wave: LVPECL single ended
10 MHz to 750 MHz reference input when used as REFI
Max input frequency when used as CKI: >= 1300 MHz

Clocking options :
Directly driven on front panel (CKI)
Synthesized by on- board Dual PLL form front panel reference clock input (REFI)
Synthesized by on-board Dual PLL from reference clock input form FMC connector

Clock Output (CKO)
SSMC connector, 50 Ohm, AC coupled
800 mV peak-peak typ., square
300 to 1300 MHz

Trigger input
SSMC connector, 50 Ohm, AC/DC coupled. LVPCELor Single ended

ADC digital interface
12 LVDS data + 1 LVDS clock
Offset binary or 2’s complement

Board Electrical/environmental
12 LVDS data + 1 LVDS clock, offset binary or 2’s complement
Board Electrical/environmental 
FMC I/O voltage: VADJ=1.8V
Power dissipation: 13.5 W

Interface features

Front board. 7 x SSMC connectors
4 x Analog Inputs
One Clock input (CKI or REFI)
One Clock output
One Trigger Input

FMC connector according to VITA 57.1:
12 LVDS data + 1 LVDS clock per channel